Managing Scratchpad Memory Architecture for Lower Power Consumption Using Programming Techniques

Kavita Tabbassum; Shahnawaz Talpur; Noor-u-Zaman Laghari

doi:10.18034/ajase.v9i1.31

Authors

Kavita Tabbassum Information Technology Centre, Sindh Agricultural University, Tando Jam, Hyderabad, Sindh, PAKISTAN
Shahnawaz Talpur Department of Computer Systems Engineering, Mehran University of Engineering & Technology, Indus Hwy, Jamshoro, Sindh, PAKISTAN
Noor-u-Zaman Laghari Department of Computer Systems Engineering, Mehran University of Engineering & Technology, Indus Hwy, Jamshoro, Sindh, PAKISTAN

Keywords:

Scratch

Scratchpad

Memory Architectures

Abstract

In embedded systems Scratch memory is generally used as an addition to caches or as a substitute of cache, but due to their comprehensive ease of programmability cache containing architectures are still to be chosen in numerous applications. Power consumption of ported applications can be significantly lowered as well as the portability of scratchpad architectures will be advanced with our suggested language-agnostic software management method. To enhance the memory configuration on relevant architectures, a variety of present methods is reviewed for finding the chances of optimizations and usage of new methods as well as their applicability to numerous memory schemes are discussed in this paper.

Downloads

Download data is not yet available.

Metrics

Metrics Loading ...

References

Bai K. and Shrivastava. A. (2000) Heap data management for limited local memory (llm) multi-core processors. In Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2010 IEEE/ACM/IFIP International Conference, pages 317-325. IEEE. DOI: https://doi.org/10.1145/1878961.1879015

Bai. K. (2014) Compiler and Runtime for Memory Management on Software Managed Manycore Processors. PhD thesis, Arizona State University.

Banakar, R.; Steinke, S.; Lee, B.-S.; Balakrishnan, M. and Marwedel, P. (2002) Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In Proceedings of the tenth international symposium on Hardware/software codesign, pages 73-78. ACM. DOI: https://doi.org/10.1145/774789.774805

Gao. Y. (2014) Automated Scratchpad Mapping and Allocation for Embedded Processors. PhD thesis, University of South Carolina - Columbia.

Grosser, T.; Groesslinger, A. and Lengauer. C. (2012) Polly performing polyhedral optimizations on a low-level intermediate representation. Parallel Processing Letters, 22(04):1250010. DOI: https://doi.org/10.1142/S0129626412500107

Kannan, A.; Shrivastava, A.; Pabalkar, A. and Lee, J.-e. (2009) A software solution for dynamic stack management on scratch pad memory. In Proceedings of the 2009 Asia and South Paci_c Design Automation Conference, pages 612-617. IEEE Press. DOI: https://doi.org/10.1109/ASPDAC.2009.4796548

Lee, J.; Kim, H. and Vuduc. R. (2012) When prefetching works, when it doesn't, and why. ACM Trans. Archit. Code Optim., 9(1):2:1-2:29. DOI: https://doi.org/10.1145/2133382.2133384

Lu, J.; Bai, K. and Shrivastava. A. (2013) Ssdm: smart stack data management for software managed multicores (smms). In Proceedings of the 50th Annual Design Automation Conference, page 149. ACM. DOI: https://doi.org/10.1145/2463209.2488918

Mattson, T. G.; Van der Wijngaart, R. and Frumkin. M. (2008) Programming the intel 80-core network-on-a-chip terascale processor. In Proceedings of the 2008 ACM/IEEE conference on Supercomputing, page 38. IEEE Press. DOI: https://doi.org/10.1109/SC.2008.5213921

Pena A.J. and Balaji. P. (2014) Toward the efficient use of multiple explicitly managed memory subsystems. In Cluster Computing (CLUSTER), 2014 IEEE International Conference on, pages 123-131. IEEE. DOI: https://doi.org/10.1109/CLUSTER.2014.6968756

Shivaraj, K. and Dharishini, P.P.P. (2015) Design and simulation analysis of time predictable computer architecture. MSRUAS-SASTech Journal, 14(1):5-8.

Verma, M.; Wehmeyer, L. and Marwedel. P. (2005) Efficient scratchpad allocation algorithms for energy constrained embedded systems. In Power-Aware Computer Systems, pages 41-56. Springer. DOI: https://doi.org/10.1007/978-3-540-28641-7_4